Projects

Designed modular CMOS basic logic gates (INV, NAND, NOR, AND, OR, XOR, MUX) using 90nm technology in HSPICE. Analyzed propagation delays across PVT variations (SS, FF, SF, FS corners and temperatures from 10°C to 70°C) and transistor sizing ratios (Beta/Wp scaling). Constructed 1-bit and 8-bit Ripple-Carry Adders using custom subcircuits and evaluated critical path delays.

Performed manual Logical Effort calculations (path branching, electrical effort, and parasitic delay) to optimize sizing for minimal propagation delay in a multi-stage combinational logic circuit using 32nm bulk PTM CMOS technology. Validated theoretical models in HSPICE, conducted parametric sweeps (using .alter) on 3-input NOR gate sizing to analyze performance vs. static/dynamic power trade-offs, and optimized total path delay by adding optimal inverter buffer stages.

Implemented modular 8-bit Ripple-Carry (RCA) and Brent-Kung Parallel-Prefix Tree Adders in 90nm CMOS HSPICE. Automated large-scale functional testing (>1000 random test vectors) and Digital Vector File (.DVF) generation via custom Python automation scripts. Conducted quantitative evaluations of worst-case critical path delay, static leakage power, and dynamic power, followed by 5-corner PVT analysis and 100-run Monte Carlo simulations for VDD supply noise and temperature variations.

Designed transistor-level D-Latches, Master-Slave D Flip-Flops, and combinational logic blocks using 180nm CMOS technology in HSPICE. Evaluated setup time ($t_{setup}$), hold time ($t_{hold}$), and clock-to-q delay ($t_{cq}$) to determine the maximum operating frequency ($f_{max}$) under Flip-Flop-bounded pipelines versus theoretical delay constraints. Partitioned combinational logic across multi-phase latches to exploit time borrowing (slack passing) and maximize system clock throughput.

Implemented Just Train Twice (JTT) and Generalized Cross-Entropy (GCE) loss functions on an MLP architecture to mitigate spurious correlations and resolve worst-group accuracy drop.

Implemented FGSM and PGD white-box attacks on ResNet-20 for CIFAR-10 alongside score-based black-box attack analysis using discrete cosine transform (DCT-SimBA).

Built LIME interpretable linear surrogates and implemented Grad-CAM / FinerGrad-CAM fine-grained saliency visualization pipelines from scratch in PyTorch for ResNet models.

Built a custom Structural Causal Model (SCM) class supporting do-calculus interventions, ATE/ATT/CATE estimations, Simpson's paradox resolution, and Bayesian network d-separation analysis.

Evaluated mathematical impossibility theorems (Chouldechova identity) and implemented pre-processing/post-processing debiasing methods alongside intersectional fairness auditing.

Implemented Laplace and Gaussian DP noise mechanisms, privacy budget analysis ($\epsilon, \delta$), Federated Learning robustness trade-offs, and membership inference attack evaluations.

This project provides a implementation of a Denoising Diffusion Probabilistic Model (DDPM) to generate images of handwritten digits. The model is trained from scratch on the well-known MNIST dataset.

This project implements a CycleGAN, a model for unpaired image-to-image translation, applied to the horse2zebra dataset.

This project implements a pix2pix Generative Adversarial Network (GAN), a type of Conditional GAN (cGAN), for image-to-image translation, specifically converting satellite images to maps. The architecture is based on the original pix2pix paper by Isola et al. (2017), using a U-Net Generator and a PatchGAN Discriminator.

This report details the implementation and evaluation of a Generative Adversarial Network (GAN) designed to generate and morph human face images.

This project implements a Variational Autoencoder (VAE) to generate human faces using the LFW (Labeled Faces in the Wild) dataset. The VAE is trained to learn a latent representation of face images and then generate new faces by sampling from this latent space.

Designed an Autoencoder for the purpose of reconstruction of damaged images using the CIFAR-10 dataset.

Designed a modular SPI master and slave supporting different CPOL and CPHA along with different packet width, enabling flexible serial communication.

Testing a four-bit counter using universal verification methodology (UVM) focusing on basic concepts, Sequencer, Driver, etc.

Designed a Super Scaler Pipeline Processor, with fully customized 32bit Instruction Set Architecture (ISA), aiming to increase the throughput.

Designed a pipelined ARM processor, exploring the differences between leveraging hazard unit and forwarding unit in terms of latency using Xilinx Vivado.

Designed modular hardware-based SHA256, aiming to accelerate hash generating built on SHA256 algorithm in the field of Cryptography using Verilog.

Design a hardware for RGB segmentation based on spiking neural networks (SNN) to detect crosswalks in the roads using Verilog and Q16.16 fixed-point binary representation.

Design both bus functional and RT level design of a Pattern Finder using CNNs (Convolutional Neural Networks) to detect specific patterns of its input image using systemC.
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Designed single-cycle, multi-cycle, and pipeline RISC-V processors in Verilog, developing instruction sets, control units, and datapaths, with strong expertise in computer architecture and instruction pipelining.
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Evaluating FIR Filters using MATLAB Simulink in order to compare the influence of floating-point and fixed-point in resource sharing.
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Designing a hardware accelerator for FIR calculation based on the NIOS II processor of Altera FPGA board.

Designing a FIR filter for the purpose of noise reduction using the integration of MATLAB and Verilog.

Designing a multiplier using Wallace Tree Algorithm using HSpice in order to find critical path and evaluate its potential violations (hold time/ setup time violation).
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Investigating the effect of gate dimensions on power consumption and delay using HSpice and required library
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Designing Leros Processor using Chisel library comparing its advantages compared to hardware description languages.
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Designed RTL architecture of a multi-channel synchronous serial demultiplexer (MSSD) in Verilog, ensuring seamless multi-channel communication with proficient logic design and synchronization.
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Developed a high-performance Selection Sorter RTL in Verilog, demonstrating expertise in efficient sorting algorithms, RTL coding, and hardware optimization.
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Designed and implemented a robust Bubble Sort hardware architecture in Verilog, optimizing sorting algorithms for performance and demonstrating proficiency in coding and hardware optimization.
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Developed a C++ program able to convert transistor level Verilog codes to “assign” statements in order to redesign existing designs using Boolean Algebra equations.
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Design a Selection Sorter Circuit (SSC) to accelerate its timing and enhance sequential circuit using systemC hardware design language.
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Layout design using L-edit and S-edit regarding certain design rules in VLSI course.
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Built a Tableau dashboard, analyzing 50K+ Airbnb listings, revealing geographic pricing host strategies, and seasonal trends using LOD calculations and interactive filters.

Built a Kafka-PySpark-MongoDB pipeline, for real-time payment processing, fraud detection, and Dash-powered analytics, handling 100+ events/min.

YOLOv3 Object Detection, developed a Jupyter Notebook implementing YOLOv3 (COCO dataset) to detect 80 object classes, drawing labeled bounding boxes with confidence scores using OpenCV.

Vehicle Speed Detection, engineered a Jupyter Notebook to track cars in videos using dlib and Haar Cascades, estimating speed (km/hr) via pixel displacement and saving annotated output.

Real-Time Object Detection (MobileNet SSD), designed a Jupyter Notebook for object detection using MobileNet SSD (21 classes), processing images, webcam feeds, and videos with bounding boxes and FPS overlay.

Face Sketch Effect for Images/Videos, implemented a Jupyter Notebook to convert images and videos into pencil sketches using OpenCV’s grayscale inversion and Gaussian blur, optimized for real-time webcam processing.

Image Alignment, developed a Jupyter Notebook to align scanned documents to reference templates using OpenCV’s homography and warpPerspective, with Matplotlib visualization.

Face Detection & Blurring, created a Jupyter Notebook leveraging OpenCV’s Caffe model to detect and dynamically blur faces in images, live webcam streams, and video files with confidence-based filtering.

artoonify Images/Videos, built a Python application in Jupyter Notebook to transform images and videos into cartoon style art using OpenCV, incorporating edge masking, bilateral filtering, and FPS visualization.

Age & Gender Detection, developed a Jupyter Notebook for real-time age and gender prediction using OpenCV and pre-trained Caffe/TensorFlow models, processing images, webcam feeds, and videos with FPS monitoring.

Image Processing and Analysis, using Jupyter Notebooks with Python libraries (PIL, OpenCV, NumPy, Matplotlib, scikit-image, and exiftool) to demonstrate image processing techniques—including transformations, metadata extraction, similarity comparison, and lesion detection.

Developed a Jupyter Notebook on convolution, kernels, and 1D and 2D filters, in the context of computer Vision and Signal processing, blending theory and practical implementations.

Designing and training a LIF model of spiking neural networks (SNN) for the purpose of RGB segmentation specified to crosswalk detection of the input image.

Designing and training a multi-layer-perceptron (MLP) from the scratch for the purpose of RGB segmentation specified to crosswalk detection of the input image.

Designed a comprehensive banking system in C++ with account management, transaction processing, and data security, utilizing object-oriented programming for modularity and extensibility.
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Developed a captivating Bomberman game in C++ with engaging mechanics, graphics, and sound effects, showcasing proficiency in game development using object-oriented programming and C++ graphics libraries, algorithms, and data structures.
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Designed a hospital reservation system in C++ for efficient appointment scheduling and management, ensuring reliability, scalability, and data integrity through sound software engineering principles.
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Developed a C++ filter app for applying effects to BMP images and saving modified versions, demonstrating expertise in image processing algorithms and file handling leveraging object-oriented programming concepts.
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Created the Spotify-like web application named Sputify in C++, applying object-oriented programming principles on music streaming, playlist management, and user authentication, showcasing skills in web development, database integration, and server-side programming.
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Designed and implemented analog and digital signal modulation methods (AM, DSB, SSB, PM, FM) in MATLAB, evaluating performance with and without noise, and developed a strong understanding of digital modulation techniques like PCM and PWM.
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